Overload protection of a transformer loaded line driver

ABSTRACT

A method of identifying and correcting each of the changes that may occur with wire pairs between the transmitter and receiver in Ethernet 10GBase-T cabling is provided. The method includes four wire pairs A, B, C and D, a polarity swapping and scrambler state machine that determine if the chosen pair matches the requirements for pair A. A slave Tap state machine generates a rule for correct B, C and D patterns based on a pair chosen as pair A. The cables B, C and D are iteratively swapped to rearrange the pair mapping into the polarity swap state machine, and a deskew state machine identifies the latency difference between the different pairs. If the rules are not satisfied, a new pair A is designated at the swapping state machine and the process is repeated until the rules are satisfied.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is a continuation of pending U.S. patent applicationSer. No. 13/087,027, filed Apr. 14, 2011, which is a divisional of U.S.application Ser. No. 12/012,725, filed Feb. 1, 2008, now abandoned,which claims priority to provisional application No. 60/900,180, filedFeb. 7, 2007. These prior applications are incorporated herein byreference, in their entirety, for any purpose.

FIELD OF THE INVENTION

The invention relates generally to electronic communication systems.More particularly, the invention relates to a training pattern to enablerecognition of proper wire-pair orientation and correction in electroniccommunication systems.

BACKGROUND

In Ethernet 10GBase-T cabling, the data is sent over four pairs ofwires. Between the transmitter and receiver, the pairs can be swappedwith each other, and the wires in a pair can be swapped. Thesereconfigurations can result in an inverted signal or the latency of thefour pairs can differ. 10GBASE-T, or IEEE 802.3an-2006, is a standard toprovide 10 gigabit/second connections over conventional unshielded orshielded twisted pair cables, over distances up to 100 m. This standardmandates specific training patterns to enable recognition of the propercorrection, but does not provide a means to find the proper correctionsfrom all the possibilities. Accordingly, there is a need to develop analgorithm to efficiently search the possible corrections and identifythe correct one.

SUMMARY OF THE INVENTION

The current invention is a method of recognizing inverted signals andlatency difference in wire pairs between a transmitter and receiver in10GBase-T Ethernet cabling due to wire pair mismatch, and correcting theinversion and latency by swapping the cable orders. The method includesproviding four pairs of wires, wherein the wires transmit data betweenthe transmitter and the receiver. The wire pairs include pairs A, B, C,and D, whereas the pairs are arranged in a quadrille pattern having twotop pairs and two bottom pairs. The method includes providing a pairswapping state machine, where the swapping state machine selects onepair from the top pairs, whereas the selected pair is designated as pairA. A polarity swapping and scrambler lock state machine is provided,where the lock state machine determines if the designated pair A is acorrect choice for position A. The lock state machine then determines ifthe selected pair is inverted. If the selection for A is not correct anext pair of the wires is designated as pair A and the determination isrepeated until the requirements for pair A are met and the pair is notinverted. A slave tap state machine is provided, where the tap statemachine establishes a rule for a correct B, C, and D pattern based onthe determined pair A. The lock state machine is used to designate asecond top pair as pair B. The lock state machine is further used todesignate a first bottom pair as pair C and to designate a first bottompair as pair D. A deskew state machine is provided, where the deskewstate machine compares all the designations over all possible latencieswith the rules generated by the slave tap machine, where if the rulesare not satisfied, the cable swap state machine reverses the designatedpair C with designated pair D. The deskew state machine is used tore-compare all the designations over all possible latencies with therules generated by the slave tap machine, where if the rules are notsatisfied, a new pair A is designated at the swapping state machine andthe process is repeated until the rules are satisfied.

DETAILED DESCRIPTION

Details of various embodiments of the present invention are disclosed inthe following appendices:

Appendix A.

Appendix B.

Appendix C.

As one of ordinary skill in the art will appreciate, various changes,substitutions, and alterations could be made or otherwise implementedwithout departing from the principles of the present invention.Accordingly, the examples and drawings disclosed herein including theappendix are for purposes of illustrating the preferred embodiments ofthe present invention and are not to be construed as limiting theinvention.

What is claimed is:
 1. A line driver circuit comprising: an outputtransistor on an integrated circuit chip, wherein the output transistoris configured to provide an output signal to a transformer coupled to aload; and an overload detector circuit on the integrated circuit chip,wherein the overload detector circuit is configured to: receive theoutput signal; compare the output signal to a threshold value range; andresponsive to the output signal having a value that is outside thethreshold value range, providing a control signal to the transistor toreduce an amplitude of the output signal.
 2. An rate adaptation systemcomprising: a first first in, first out (FIFO) buffer configured toserially receive a first plurality data blocks via a first data bus at arate based on a first clock, the first FIFO buffer further configured tooutput the first plurality of data blocks in an order receivedresponsive to valid read requests of a plurality of read requests, at arate based on a second clock; a rate adaptation transmit registerconfigured to serially provide a second plurality of data blocks from asecond FIFO buffer to a second data bus at a rate based on the secondclock, wherein a frequency of the first clock is greater than afrequency of the second clock; and a barrel shift slot registerconfigured to, responsive to the first clock, provide the firstplurality of data blocks from the first FIFO buffer to the second FIFObuffer at a rate based on the second clock.